A memory comprises a network of memory cells organized in matrix form in columns and in rows.The memory cells of one and the same column are connected to a bit line and the memory cells of one and the same row are connected to a word line. During a reading stage, the bit line delivers an information element on the state of the memory cell at the intersection of the bit line and a selected word line.
The read circuits are connected to the bit lines either directly or, more generally, by means of a multiplexer used to associate a read circuit with several bit lines. Only one bit line is described as associated with the read circuit to simplify the explanation as follows. The working of a read circuit can generally be sub-divided into three stages: a bit line pre-charging stage, a balancing stage and a memory cell reading stage. Hereinafter, it should be assumed that the memory is an EEPROM whose cells may have an erased state in which they pass an electrical current, or a programmed state in which they hinder the passage of a current. To read an information element on the state of the selected cell, it is desired to detect the presence of a current in the bit line connected to the selected cell. And a current of this kind exists if the cell is erased or blank, and it does not exist if the cell is programmed.
To detect the presence of this current, a bit line connected to blank cells called reference cells is used. This bit line, called a reference line, carries a reference current during the reading stage. During the pre-charging stage, the bit line connected to the memory cell to be read and the reference line are taken to a reference potential. The balancing stage that follows enables the balancing of the potential of the two bit lines. Then, during the reading stage, the current of the bit line is compared with the reference current. The result of this comparison makes it possible to find out-the state of the cell read. This comparison is generally made by a differential amplifier preceded by a current/voltage converter.
FIG. 1 gives a simplified view of an exemplary prior art read circuit. For the sake of greater clarity, this Figure does not describe the mechanisms for balancing the bit lines. A memory cell CM comprising a selection transistor TS series connected with a floating-gate transistor TGF is connected to a bit line LB. The gate of the selection transistor TS is connected to a word line LM, while the gate of the floating-gate transistor TGF is connected to a read line LL to which there is applied a read voltage VL during the reading phase. At the end of the reading operation, the information representing the state of the memory cell CM is delivered on the bit line LB.
Similarly, a reference cell CR comprising a selection transistor TSR and a floating-gate transistor TGFR is connected to a reference line LR. The gate of the selection transistor TSR is also connected to the word line LM and the gate of the floating-gate transistor TGFR is connected to a read line LLR to which there is applied the read voltage VL during the reading stage. During the pre-charging stage, the two bit lines LB and LR are pre-charged at a reference value of about 1 volt respectively by means of the pre-charging transistors T1 and T2. These transistors T1 and T2 have the function of respectively giving a pre-charging current to the two bit lines LB and LR, while at the same time limiting the reference voltage to a predetermined value close to one volt.
Indeed, if the reference voltage of the line is too high, there is a risk of parasitic programming of the memory cell CM attached to the bit line LB. If the reference voltage is too low, the current flowing in the bit line LB will not be high enough to obtain sufficiently fast reading of the memory cell CM.
The transistors T1 and T2 are preferably N channel natural transistors and their sources are connected respectively to the bit line LB and to the reference line LR. To simplify the drawing, the pre-charging circuit is shown in the form of a feedback block CTR connecting the gate of the transistors T1 and T2 to the source of the transistor T1. The role of this feedback block is to provide a sufficient pre-charging voltage Vp to the gate of the transistors T1 and T2 to pre-charge the bit lines LB and LR at the reference voltage.
Furthermore, the drains of the transistors T1 and T2 are connected to the two arms of a current mirror. The first arm has a P-channel reference transistor T3 having its drain and its gate connected to each other (in a diode configuration) and its source connected to a supply terminal Vcc. Its drain is furthermore connected to the drain of the pre-charging transistor T1. The second arm of the current mirror is provided by a P-channel transistor which mirrors transistor T4. Transistor T4 has its gate connected to the gate and drain of the transistor T3, with its source connected to the supply terminal Vcc and its drain connected to the drain of the transistor T2.
To make it easier to understand the explanations that follow, the drain of the reference transistor T3 is indicated by the point A, its gate by the point B, and the source of the transistor T1 by the point C.
Finally, a differential amplifier AD has its inputs connected to the drains of the transistors T3 and T4 and measures the difference between the potentials at these two drains. The output of the amplifier AD produces a signal that indicates whether the difference is positive or negative.
This type of circuit works well when it is supplied with a supply voltage in the range of 5 volts. However, it has the drawback of being unsuited for memories supplied with a voltage in the range of about 1.8 volts. Indeed, in the latter case, when the reference transistor T3 is conductive, the potential at the point A is at most equal to 1 volt if it is assumed that the threshold voltage Vt of the reference transistor T3 is equal to 0.8 volts. It is then difficult to maintain a stable potential of about 1 volt at the point C during the pre-charging phase if it is assumed in addition that the current flowing in the reference line LR will contribute to further lowering of the potential at the point C.